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Low Power, High Output Current, Quad Op Amp, Dual-Channel ADSL/ADSL2+ Line Driver
AD8392A
FEATURES
Four current feedback, high current amplifiers Ideal for use as ADSL/ADSL2+ dual-channel central office (CO) line drivers Low power operation Power supply operation from 5 V (+10 V) up to 12 V (+24 V) Less than 3 mA/amp quiescent supply current for full power ADSL/ADSL2+ CO applications (20.4 dBm line power, 5.5 CF) Three active power modes plus shutdown High output voltage and current drive 500 mA peak output drive current 42.6 V p-p differential output voltage Low distortion -93 dBc @1 MHz second harmonic -103 dBc @ 1 MHz third harmonic High speed: 515 V/s differential slew rate Additional functionality of AD8392AACP On-chip, common-mode voltage generation
PIN CONFIGURATIONS
VEE 1 PD0 1, 2 PD1 1, 2 +VIN1 -VIN1 VOUT1 VCC NC VOUT3
2 3 4 5 6 7 8 9 28 GND 27 NC 26 NC
1
2
25 +VIN2 24 -VIN2 23 VOUT2
AD8392A
22 NC 21 VCC 20 VOUT4 19 -VIN4 18
-VIN3 10 +VIN3 11 NC 12 NC 13 GND 14
3
4
+VIN4 PD0 3, 4
06477-001
17 PD1 3, 4 16 15
VEE
NC = NO CONNECT
Figure 1. AD8392AARE, 28-Lead TSSOP/EP
PD1 1, 2
PD0 1, 2
+VIN1
VCOM1, 2
APPLICATIONS
ADSL/ADSL2+ CO line drivers XDSL line drives
NC 1 -VIN1 VOUT1 VCC NC VOUT3 -VIN3 NC
2 3 4 5 6 7 8
32 31 30 29 28 27 26 25
+VIN2
24 23 22
VEE
GND
NC
1
2
NC -VIN2 VOUT2 NC VCC VOUT4 -VIN4 NC
GENERAL DESCRIPTION
The AD8392A is comprised of four high output current, low power consumption, operational amplifiers. It is particularly well suited for the CO driver interface in digital subscriber line systems, such as ADSL and ADSL2+. The driver is capable of providing enough power to deliver 20.4 dBm to a line, while compensating for losses due to hybrid insertion and back termination resistors. The AD8392A is available in two thermally enhanced packages, a 28-lead TSSOP/EP (AD8392AARE) and a 5 mm x 5 mm, 32-lead LFCSP (AD8392AACP). Four bias modes are available via the use of two digital bits (PD1, PD0). Additionally, the AD8392AACP provides VCOM pins for on-chip, common-mode voltage generation. The low power consumption, high output current, high output voltage swing, and robust thermal packaging enable the AD8392A to be used as the CO line drivers in ADSL and other xDSL systems.
AD8392A
21 20 19
3
9
4
18 17
10 11 12 13 14 15 16
VCOM3, 4
+VIN3
PD0 3, 4
PD1 3, 4
+VIN4
GND
NC
VEE
NC = NO CONNECT
Figure 2. AD8392AACP, 5 mm x 5 mm, 32-Lead LFCSP
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved.
06477-002
AD8392A TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Pin Configurations ........................................................................... 1 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 4 Thermal Resistance ...................................................................... 4 ESD Caution.................................................................................. 4 Typical Performance Characteristics ............................................. 5 Theory of Operation ........................................................................ 7 Applications........................................................................................8 Supplies, Grounding, and Layout................................................8 Power Management ......................................................................8 Thermal Considerations...............................................................8 Typical ADSL/ADSL2+ Application...........................................9 Multitone Power Ratio............................................................... 10 Outline Dimensions ....................................................................... 11 Ordering Guide .......................................................................... 11
REVISION HISTORY
10/06--Revision 0: Initial Version
Rev. 0 | Page 2 of 12
AD8392A SPECIFICATIONS
VS = 12 V or +24 V, RL = 100 , G = +5, PD = (0, 0), T = 25C, unless otherwise noted. Table 1.
Parameter DYNAMIC PERFORMANCE -3 dB Small Signal Bandwidth -3 dB Large Signal Bandwidth Peaking Slew Rate NOISE/DISTORTION PERFORMANCE Second Harmonic Distortion Third Harmonic Distortion Multitone Input Power Ratio Voltage Noise (RTI) +Input Current Noise -Input Current Noise INPUT CHARACTERISTICS RTI Offset Voltage +Input Bias Current -Input Bias Current Input Resistance Input Capacitance Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Differential Output Voltage Swing Single-Ended Output Voltage Swing Linear Output Current POWER SUPPLY Operating Range (Dual Supply) Operating Range (Single Supply) Total Quiescent Current PD1, PD0 = (0, 0) PD1, PD0 = (0, 1) PD1, PD0 = (1, 0) PD1, PD0 = (1, 1) (Shutdown State) PD = 0 Threshold PD = 1 Threshold +Power Supply Rejection Ratio -Power Supply Rejection Ratio Min 25 23 Typ 37 30 0.06 515 -93 -103 70 2.5 7.6 12.5 -4 2 2 3 8 1 66 42.6 21.3 500 12 24 5.8 3.0 2.6 0.4 1.8 72 65 6.5 3.5 3.0 0.08 0.8 +4 7 10 Max Unit MHz MHz dB V/s dBc dBc dBc nV/Hz pA/Hz pA/Hz mV A A M pF dB V p-p V p-p mA V V mA/amp mA/amp mA/amp mA/amp V V dB dB Test Conditions/Comments VOUT = 0.1 V p-p, RF = 2 k VOUT = 4 V p-p, RF = 2 k VOUT = 0.1 V p-p, RF = 2 k VOUT = 20 V p-p, RF = 2 k fC = 1 MHz, VOUT = 2 V p-p fC = 1 MHz, VOUT = 2 V p-p 26 kHz to 2.2 MHz, ZLINE = 100 differential load f = 10 kHz f = 10 kHz f = 10 kHz V+IN - V-IN
63 41.2 20.6
(VOS, DM (RTI))/(VIN, CM) VOUT VOUT, RL = 50 RL = 10 , fC = 100 kHz
5 10
74 69
VOS, DM (RTI)/VCC, VCC = 1 V VOS, DM (RTI)/VEE, VEE = 1 V
Rev. 0 | Page 3 of 12
AD8392A ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Supply Voltage Power Dissipation Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering 10 sec) Junction Temperature Rating 13 V (+26 V) See Figure 3 -65C to +150C -40C to +85C 300C 150C
RMS output voltages should be considered. If RL is referenced to VS- as in single-supply operation, the total power is VS x IOUT. In single supply with RL to VS-, worst case is VOUT = VS/2. Airflow increases heat dissipation, effectively reducing JA. In addition, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes reduces the JA. Figure 3 shows the maximum safe power dissipation in the package vs. the ambient temperature for the LFCSP-32 and TSSOP-28/EP packages on a JEDEC standard 4-layer board. JA values are approximations.
7 TJ = 150C 6 5 LFCSP-32 4 3 2 1 0 -40 -30 -20 -10 TSSOP-28/EP
THERMAL RESISTANCE
JA is specified for the worst-case conditions, that is, JA is specified for the device soldered in the circuit board for surface-mount packages. Table 3.
Package Type LFCSP-32 (CP) TSSOP-28/EP (RE) JA 27.27 35.33 Unit C/W C/W
MAXIMUM POWER DISSIPATION (W)
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
0
Maximum Power Dissipation
The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). Assuming that the load (RL) is midsupply, the total drive power is VS/2 x IOUT, some of which is dissipated in the package and some in the load (VOUT x IOUT).
10 20 30 40 50 TEMPERATURE (C)
60
70
80
90
Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
See the Thermal Considerations section for additional thermal design guidance.
ESD CAUTION
Rev. 0 | Page 4 of 12
06477-003
AD8392A TYPICAL PERFORMANCE CHARACTERISTICS
900 850 -20 0
POWER CONSUMPTION (mW)
750 700
PD (0, 0)
SIGNAL FEEDTHROUGH (dB)
06477-046
800
-40
PD (0, 1) 650 600 550 500 PD (1, 0)
-60
-80
-100
16
17
18
19
20
21
1M
10M FREQUENCY (Hz)
100M
1G
OUTPUT POWER (dBm)
Figure 4. Power Consumption vs. Output Power (138 kHz to 2.2 MHz), ADSL/ADSL2+ Circuit (Figure 15), VS = 12 V, RLOAD = 100 , CF = 5.5
15 10 5
Figure 7. Signal Feedthrough vs. Frequency VS = 12 V, G = +5, VIN = 800 mV p-p, PD (1, 1), RF = 2 k
PD (0, 0)
GAIN (dB)
PD (0, 1) 0
2
-5 PD (1, 0) -10
1
-15 -20 10k
06477-042
06477-041
100k
1M
10M
100M
1G
06477-049
CH1 500mV CH2 500mV
100ns
FREQUENCY (Hz)
Figure 5. Small Signal Frequency Response VS = 12 V, RLOAD = 100 , G = +5, VOUT = 100 mV p-p, RF = 2 k
15 10 PD (0, 0) 5
Figure 8. Power-Up Time: PD (1, 1) to PD (0, 0) VS = 12 V, RLOAD = 100 , G = +5, VOUT = 1 V p-p, RF = 2 k
GAIN (dB)
0
2
-5 PD (0, 1) -10 PD (1, 0) -15 -20 10k
1
100k
1M
10M
100M
1G
06477-045
CH1 500mV CH2 500mV
400ns
FREQUENCY (Hz)
Figure 6. Large Signal Frequency Response VS = 12 V, RLOAD = 100 , G = +5, VOUT = 4 V p-p, RF = 2 k
Figure 9. Power-Down Time: PD (0, 0) to PD (1, 1) VS = 12 V, RLOAD = 100 , G = +5, VOUT = 1 V p-p, RF = 2 k
Rev. 0 | Page 5 of 12
06477-048
450 15
-120 100k
AD8392A
100
INPUT CHANNEL 1
OUTPUT IMPEDANCE ()
OUTPUT CHANNEL 2
10
1
PD (0, 0)
2
0.1
PD (1, 0)
PD (0, 1)
06477-040
CH1 200mV CH2 2V
400ns
100k
1M
10M
100M
1G
FREQUENCY (Hz)
Figure 10. Output Overdrive Recovery, ADSL/ADSL2+ Circuit (Figure 15), DMT Waveform, VS = 12 V
0 -10 -20
Figure 13. Output Impedance vs. Frequency VS = 12 V, G = +5, RF = 2 k
CROSSTALK (dB)
-30 -40 -50 -60 -70 -80 -90 1M 10M FREQUENCY (Hz) 100M
06477-025
DIFF CHANNEL 1, 2
49.9
DIFF CHANNEL 3, 4
2k 499 2k 100
-100 100k
49.9
Figure 11. Crosstalk vs. Frequency, Dual Differential Driver Circuit (Figure 14), VS = 12 V, VIN = 800 mV p-p
45 40
Figure 14. Dual Differential Driver Circuit
1.78k
DIFFERENTIAL OUTPUT (V p-p)
35
0.01F
30
634 4.99 77 87 2k VCM 77 87 1F 2k 100
25 20 15 10
0.01F 634
0 10 20 30 40 50 60 70 80 90 100
06477-054
4.99
06477-053
LOAD RESISTANCE ()
1.78k
Figure 12. Differential Output Swing vs. RLOAD Dual Differential Driver Circuit (Figure 14)
Figure 15. ADSL/ADSL2+ Circuit
Rev. 0 | Page 6 of 12
06477-021
06477-047
0.01 10k
AD8392A THEORY OF OPERATION
The AD8392A is a current feedback amplifier with high (500 mA) output current capability. With a current feedback amplifier, the current into the inverting input is the feedback signal, and the open-loop behavior is that of a transimpedance, dVO/dIIN or TZ. The open-loop transimpedance is analogous to the open-loop voltage gain of a voltage feedback amplifier. Figure 16 shows a simplified model of a current feedback amplifier. Because RIN is proportional to 1/gm, the equivalent voltage gain is TZ x gm, where gm is the transconductance of the input stage. Basic analysis of the follower with gain circuit yields
Of course, for a real amplifier there are additional poles that contribute excess phase, and there is a value for RF below which the amplifier is unstable. Tolerance for peaking and desired flatness determines the optimum RF in each application.
RF RG RIN IIN RN
06477-022
TZ
VOUT
VIN
VO TZ (S ) = Gx VIN TZ (S ) + G x RIN + RF
where:
Figure 16. Simplified Block Diagram
G = 1+ R IN =
RF RG
1 50 gm
The AD8392A is capable of delivering 500 mA of output current while swinging to within 2 V of either power supply rail. The AD8392A also has a power management system included on-chip. It features four user-programmable power levels (three active power modes as well as the provision for complete shutdown).
Because G x RIN << RF for low gains, a current feedback amplifier has relatively constant bandwidth vs. gain, the 3 dB point being set when |TZ| = RF.
Rev. 0 | Page 7 of 12
AD8392A APPLICATIONS
SUPPLIES, GROUNDING, AND LAYOUT
The AD8392A can be powered from either single or dual supplies, with the total supply voltage ranging from 10 V to 24 V. For optimum performance, a well regulated low ripple supply should be used. As with all high speed amplifiers, close attention should be paid to supply decoupling, grounding, and overall board layout. Low frequency supply decoupling should be provided with 10 F tantalum capacitors from each supply to ground. In addition, all supply pins should be decoupled with 0.1 F quality ceramic chip capacitors placed as close as possible to the driver. An internal low impedance ground plane should be used to provide a common ground point for all driver and decoupling capacitor ground requirements. Whenever possible, separate ground planes should be used for analog and digital circuitry. High speed layout techniques should be followed to minimize parasitic capacitance around the inverting inputs. Some practical examples of these techniques are keeping feedback traces as short as possible and clearing away ground plane in the area of the inverting inputs. Input and output traces should be kept short and as far apart from each other as practical to avoid crosstalk. When used as a differential driver, all differential signal traces should be kept as symmetrical as possible. The information in Table 3 and Figure 3 is based on a standard JEDEC 4-layer board and a maximum die temperature of 150C. To provide additional guidance and design suggestions, a thermal study was performed under a set of conditions more closely aligned with an actual ADSL/ADSL2+ application. In a typical ADSL/ADSL2+ line card, component density usually dictates that most of the copper plane used for thermal dissipation be internal. Additionally, each ADSL/ADSL2+ port may be allotted only 1 square inch, or even less, of board space. For these reasons, a special thermal test board was constructed for this study. The 4-layer board measured approximately 4 inches x 4 inches and contained two internal 1 oz copper ground planes, each measuring 2 inches x 3 inches. The top layer contained signal traces and an exposed copper strip 1/4 inch x 3 inches to accommodate heat sinking, with no other copper on the top or bottom of the board. Three 28-lead TSSOPs were placed on the board representing six ADSL channels, or one channel per square inch of copper, with each channel dissipating 700 mW on-chip (1.4 W per package). The die temperature is then measured in still air and in a wind tunnel with calibrated airflow of 100 LFM, 200 LFM, and 400 LFM. Figure 17 shows the power dissipation vs. the ambient temperature for each airflow condition. The figure assumes a maximum die temperature of 135C. No heat sink was used.
4.5 TJ = 135C 4.0 400LFM
POWER MANAGEMENT
The AD8392A can be configured in any of three active bias states as well as a shutdown state via the use of two sets of digitally programmable logic pins. Pin PD0 (1, 2) and Pin PD1 (1, 2) control Amplifier 1 and Amplifier 2, while PD0 (3, 4) and Pin PD1 (3, 4) control Amplifier 3 and Amplifier 4. These pins can be controlled directly with either 3.3 V or 5 V CMOS logic by using the GND pins as a reference. If left unconnected, the PD pins float low, placing the amplifier in the full bias mode. Refer to the Specifications for the per amplifier quiescent current for each of the available bias states. As is shown in Figure 13, the AD8392A exhibits low output impedance for the three active states. The shutdown state (PD1, PD0 = 1, 1) provides a high impedance output.
POWER DISSIPATION (W)
3.5 200LFM 3.0 2.5 STILL AIR 2.0 1.5 1.0 100LFM
5
15
25 35 45 55 65 AMBIENT TEMPERATURE (C)
75
85
THERMAL CONSIDERATIONS
When using a quad, high output current amplifier, such as the AD8392A, special consideration should be given to system level thermal design. In applications such as the ADSL/ADSL2+, the AD8392A could be required to dissipate as much as 1.4 W or more on-chip. Under these conditions, particular attention should be paid to the thermal design to maintain safe operating temperatures on the die. To aid in the thermal design, the thermal information in the Thermal Resistance section can be combined with what follows here.
Figure 17. Power Dissipation vs. Ambient Temperature and Air Flow 28-Lead TSSOP/EP
This data is only provided as guidance to assist in the thermal design process. Due diligence should be performed with regards to power dissipation because there are many factors that can affect thermal performance.
Rev. 0 | Page 8 of 12
06477-051
AD8392A
TYPICAL ADSL/ADSL2+ APPLICATION
In a typical ADSL/ADSL2+ application, a differential line driver is used to take the signal from the analog front end (AFE) and drive it onto the twisted pair telephone line. Referring to the typical circuit representation in Figure 18, the differential input appears at VIN+ and VIN- from the AFE, while the differential output is transformer coupled to the telephone line at tip and ring. The common-mode operating point, generally midway between the supplies, is set through VCOM.
R3 VIN+ R4 VP RBIAS RIN VCOM RBIAS R4 VP VOA Rm R2 1:N R1 R2 Rm VOA
06477-024
Additional definitions for calculating resistor values include:
Value Definition VOA Voltage at the amplifier outputs k Matching resistance reduction factor AV Gain from VIN to transformer primary Negative feedback factor Positive feedback factor Note: R1 must be calculated before and .
VOA =
TIP
VLINE (1 + k ) N
k=
2 Rm RL
AV =
VLINE N VIN
=
ROUT
R1 R1 + 2 R2
= (1 - k )
With the above known quantities and definitions, the remaining resistors can readily be calculated.
RING
VIN-
R1 =
2VP R2 VOA - VP
R3
Figure 18. Typical ADSL/ADSL2+ Application Circuit
R4 =
R3 =
R IN (VIN - VP ) 2 VIN
In ADSL/ADSL2+ applications, it is common practice to conserve power by using positive feedback to synthesize the output resistance, thereby lowering the required ohmic value of the line matching resistors, Rm. The circuit in Figure 18 is somewhat unique in that the positive feedback introduced via R3 has the effect of synthesizing the input resistance as well. The following definitions and equations can be used to calculate the resistor values necessary to obtain the desired gain, input resistance, and output resistance for a given application. For simplicity, the following calculations assume a lossless transformer. The following values are used in the design equations and are assumed already known or chosen by the designer.
Value VIN RIN N VLINE Rm R2 VP RL Definition Differential input voltage Desired differential input resistance Transformer turns ratio Differential output voltage at tip and ring Each is typically 5% to 15% of the transformer reflected line impedance Recommended in the amplifier data sheet Voltage at the + inputs to the amplifier, approximately 1/2 VIN (must be less than VIN for positive input resistance) Transformer reflected line impedance
AV R4 (2 R1 Rm + R1 RL - R1 RL - 2 R2 RL ) RL (R1 + 2 R2 )
R BIAS =
R3 R4 R4 - (R3 + R4 )
After building the circuit with the closest 1% resistor values, the actual gain, input resistance, and output resistance can be verified with the following equations.
GAIN (VIN to LINE ) = N R4 R4 R4 (k + 1)1 + + - R3 R BIAS R3

R IN =
2 2 Rm + RL 1 - AV R4 RL R4
ROUT =
2 Rm N 2 R4 R BIAS R1 + 2R2 1- R1(R4 + R BIAS ) R4 R BIAS R3 + R4 + R BIAS
Rev. 0 | Page 9 of 12
AD8392A
MULTITONE POWER RATIO
The DMT signal used in ADSL/ADSL2+ systems carries data in discrete tones or bins, which appear in the frequency domain in evenly spaced 4.3125 kHz intervals. In applications using this type of waveform, multitone power ratio (MTPR) is a commonly used measure of linearity. MTPR is defined as the measured difference from the peak of one tone that is loaded with data to the peak of an adjacent tone that is intentionally left empty. Figure 19 and Figure 20 show the AD8392A MTPR for a 5.5 crest factor waveform for empty bins in the ADSL and extended ADSL2+ bandwidths.
0 -10 -20 -30 -40 (dBm) -50 -60 -70 -80 -90 -100 0 -10 -20 -30 -40 (dBm) -50 -60 -70 -80 -90 -100 CENTER 646.9kHz SPAN 10kHz
06477-043
CENTER 1.9664kHz
SPAN 10kHz
Figure 20. MTPR at 1.966 MHz
Figure 19. MTPR at 647 kHz
Rev. 0 | Page 10 of 12
06477-044
AD8392A OUTLINE DIMENSIONS
9.80 9.70 9.60 3.55 3.50 3.45
28
15
4.50 4.40 4.30
1 14
6.40 BSC
EXPOSED PAD (Pins Up)
3.05 3.00 2.95
TOP VIEW 1.20 MAX 0.15 0.05 1.05 1.00 0.80 0.65 BSC 0.30 0.19
BOTTOM VIEW
8 0 0.20 0.09 0.75 0.60 0.45
050806-A
SEATING PLANE COPLANARITY 0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AET
Figure 21. 28-Lead Thin Shrink Small Outline with Exposed Pad [TSSOP/EP] (RE-28-1) Dimensions shown in millimeters
5.00 BSC SQ
0.60 MAX 0.60 MAX
25 24 32 1
PIN 1 INDICATOR
PIN 1 INDICATOR TOP VIEW 4.75 BSC SQ
0.50 BSC
EXPOSED PAD (BOTTOM VIEW)
17 16 8
3.25 3.10 SQ 2.95
0.50 0.40 0.30 12 MAX
9
0.25 MIN 3.50 REF
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM
1.00 0.85 0.80
SEATING PLANE
0.30 0.23 0.18
0.20 REF
COPLANARITY 0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 22. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm x 5 mm Body, Very Thin Quad (CP-32-2) Dimensions shown in millimeters
ORDERING GUIDE
Model AD8392AAREZ 1 AD8392AAREZ-RL1 AD8392AAREZ-R71 AD8392AACPZ-R21 AD8392AACPZ-RL1 AD8392AACPZ-R71
1
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Description 28-Lead Thin Shrink Small Outline Package (TSSOP/EP) 28-Lead Thin Shrink Small Outline Package (TSSOP/EP) 28-Lead Thin Shrink Small Outline Package (TSSOP/EP) 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
Package Option RE-28-1 RE-28-1 RE-28-1 CP-32-2 CP-32-2 CP-32-2
Z = Pb-free part.
Rev. 0 | Page 11 of 12
AD8392A NOTES
(c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06477-0-10/06(0)
Rev. 0 | Page 12 of 12

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